This invention relates to programmable logic arrays which utilize an MOS EPROM field effect transistor within the storage cell (EPROM cell) at each "intersection" of the array.
FIG. 1A shows a typical prior art implementation of a programmable logic array (PLA) which uses an MOS (metal-oxide-semiconductor) EPROM (Electrically Programmable Read Only Memory) field effect transistor in each storage cell. FIG. 1A shows the well known grid formed by a plurality of input terms, shown vertically, which "intersect" with a plurality of product terms (there is, of course, no literal electrical connection between input term and product term at the intersection). At the "intersections" of an input term and a product term, there is a programmable storage cell which may be referred to as an EPROM cell since the prior art cell uses an EPROM transistor to store and retrieve data. Thus, at the "intersection" of product term 15 (P.T.1) and input term 10 (I.T.1) there is an EPROM cell which contains an EPROM device 14a. It can be seen from FIG. 1A that the source of each EPROM transistor is coupled to Vss (labelled "17"), which is typically ground. The drain of each of these EPROMs, such as EPROMs 14a and 14b, is coupled to a product term; thus, EPROM 14b has its drain coupled to product term 15 which is also referred to as product term (P.T.1). Each EPROM in FIG. 1A, such as EPROM 14h, includes a floating gate 9 which stores binary data having two possible states and further includes a gate. The operation and structure of this prior art programmable logic array is well known in the art. See, for example, U.S. Pat. Nos. 4,124,899; 4,609,986 and 4,617,479 and the references cited in those patents; also see pages 4-1 through 4-61 of CMOS Data Book of Cypress Semiconductor Corporation (3901 North First Street, San Jose, California, 95134); and Programmable Logic Handbook, 1987, of Intel Corportation (3065 Bowers Avenue, Santa Clara, California, 95051; order no. 296083-002).
FIG. 1B shows another embodiment of a PLA in the prior art where each EPROM cell, such as EPROM cell 20, includes two EPROM MOS field effect transistors, one of which is employed to write to the EPROM cell by charging the floating gate 33 and the other of which is employed to read the state of the floating gate 33. In each EPROM cell, the floating gate 33 is common to both the write transistor, each as EPROM 31a, and the read EPROM transistor such as 30a. As is well known in the art, each product term produces a logical AND or NOR result. The embodiment shown in FIG. 5 shows the "AND" function (result) represented by AND gates 177. Each AND gate represents the logical AND result (only if all inputs are logically inverted before applying the inputs to the input pins shown in FIG. 5; otherwise, each product term actually performs a NOR logical function) which is produced by each product term. Some product terms are coupled to a NOR gate, such as NOR gate 178, which produces the well known (inverted) sum of products. Other product terms are coupled to an OR gate, such as OR gate 178b which produces the sum of products. An inverter 301 is shown coupled to Input 1 pin (IN1) of the PLA chip in FIG. 5, such an inverter will logically invert the input to the inverter, thereby producing the logically inverted input at the input 1 pin (IN1) of FIG. 5. It is understood that a PLA chip, such as that shown in FIG. 5, will normally include a plurality of product terms each of which represents a logical AND gate (if all inputs are logically inverted), such as AND gate 177, and each product term is coupled to an OR 178b gate or a NOR gate, such as NOR gate 178 or 29. It is also appreciated that many variations in the logical functions in the array and in the outputs and inputs may be used, as is well known in the art. For example, input buffers and output buffers may be employed along with flip-flops, multiplexers and other controls in the output section of a PLA, which controls are often referred to as an output macrocell (see, e.g., pages 4-39 of CMOS Data Book).
Programming of a PLA, such as that shown in FIG. 1B, is accomplished in the well known manner of applying selectively a "super voltage" (e.g. 10-25 V, which is referred to as the programming voltage V.sub.pp) to a particular input term and at the same time applying a super voltage to a write product term for a particular row (product term). For example, to program the EPROM cell 20 shown in FIG. 1B, a super voltage is applied to input term 21 while, at the same time, a super voltage is also applied to the write product term 32 (WPT1) which is bussed parallel with the read product term 25. When the super voltage is applied to input term 21 and to WPT1 (write product term 32) it will cause the super voltage to be applied to the gate of the EPROM 31a while, on WPT1, the super voltage is applied to the drain of EPROM 31a causing that EPROM MOS transistor to conduct significant current (through the current path of that EPROM between its source and drain) such that hot electrons, as is well known in the art, are driven from the channel region of EPROM 31a into the floating gate 33 which is contiguous with the floating gate of EPROM 30a. These hot electrons become trapped on the floating gate 33 of the EPROM 31a and 30a; these trapped electrons on the floating gate program the read EPROM 30a such that, under normal operating conditions no appreciable current will flow through EPROM 30a. When the floating gate of an EPROM becomes charged, that EPROM is referred to as a programmed EPROM and the cell containing that EPROM has also been programmed.
As a consequence of programming, the binary status of the read product term 25 will not be affected (e.g. pulled down to ground) by EPROM 30a once it is programmed by storing electrons on the floating gate 33. If an EPROM cell is left unprogrammed (the state when the floating gate of the EPROM is left uncharged) then it is possible for appreciable current to flow through the read EPROM transistor, which current will pull down the read product term 25 to ground (even if all other EPROMs along that product term are not conducting). If no read EPROMs along the row formed by read product term 25 are on, then the read product term 25 will be pulled substantially high (e.g. "binary 1") by the pull-up device 34 which may be an N-channel MOS field effect transistor having its gate and drain coupled to a circuit supply voltage, Vcc, which is often 5 V in the typical MOS chip. The source of pull-up device 34 is coupled to the read product term, as shown in FIG. 1B. Other embodiments of the pull-up device 34 which may be implemented by those skilled in the art include N-channel depletion devices, resistors, and P-channel devices.
It is understood that the selective programming of each of these EPROM cells enables a specific logic function to be implemented by the user as is well known in the art. Each product term represents a "product" (the result of an AND gate) which is then summed with other "products" from other product terms through the OR 178b or NOR 178 gates. It will be appreciated that any one of the read EPROM devices which are coupled to read product term 25 (e.g. EPROMs 30a, 30b or 30c) should be capable of pulling down the read product term 25 to ground even if the other read EPROM transistors along read product term 25 are off. The architecture of the PLAs shown in FIG. 1B and FIG. 5 uses a field programmable "AND" (or NOR) array which is non-programmably coupled to specified OR or NOR gates; that is, outputs from a subgroup of product terms are nonprogrammably connected as inputs to individual, specified OR (or NOR) gates to produce the "sum of the products". This architecture may be advantageously used with the present invention.
The prior art EPROM cells in programmable logic arrays use the EPROM transistors to directly drive the cell output which is coupled to the product term. This output is usually a very high capacitance node since it connects to the product term which is connected to many other EPROM cells as well as sensing circuits which amplify the signal. The naturally high impedance of an EPROM MOS transistor combined with the large capacitance on the cell output results in a long switching time on the product term node. This long switching time results in slower performance integrated circuits which utilize programmable logic arrays. It is an object of the present invention to provide an improved EPROM storage cell which provides much faster switching times by using a non-EPROM MOS field effect transistor having a low impedance to directly drive the cell output--i.e. to directly drive (modulate) the product term. The low impedance MOS transistor is turned on based on the status of the input term as well as the program state of an EPROM transistor which acts to modulate the non-EPROM MOS field effect transistor which drives the cell output.